Method for Manufacturing a Semiconductor Substrate

ABSTRACT

A method for manufacturing a semiconductor substrate includes providing a first wafer having a first surface and a second surface opposite the first surface, forming cavities in the first wafer at a first distance from the first surface, wherein the cavities, when seen in a cross-section perpendicular to the first surface, are laterally spaced from each other by partition walls formed by the semiconductor material of the first wafer, the cavities forming a separation region, bonding a second wafer on the first surface of the first wafer, breaking the partition walls by applying mechanical impact to the partition walls to split the first wafer along the separation region so that a residual wafer remains attached to the second wafer, and depositing an epitaxial layer on the residual wafer.

TECHNICAL FIELD

Embodiments described herein relate to methods for manufacturing asemiconductor substrate and methods for manufacturing semiconductordevices integrated in a semiconductor substrate.

BACKGROUND

For integrated devices, particularly power devices, suitably adaptedsemiconductor substrates are needed. Power devices, for example verticalpower devices, need semiconductor substrates with a minimal thickness towithstand the rated blocking voltage. The minimal thickness may be, forexample 60 μm. On the other hand, during processing of the semiconductorsubstrate, a higher thickness, for example 600 μm, is desired formechanical stability. Thick substrates, however, have a high electricaland thermal resistance which may affect the electrical performance ofthe final devices. After integrating the devices, the substrates aretherefore thinned to reduce these resistances.

For cost reasons, typically mechanical or chemical etching and polishingprocesses are employed for reducing the thickness. As these processesexhibit intrinsic thickness variations of the processed substrates,other processes having pre-defined etch or polishing steps are employedto avoid such variations. For example, buried pn-junctions can be usedas etch step. Furthermore, change of material properties or differentmaterial combinations can also be used either as etch stop or as layerwhich allows a separation of substrates. Such “separation layers” mustwithstand the processing conditions during integration of the devices.

Other approaches uses laser light to generate separation regions in agiven distances from the substrate surface. Such processes, however, arevery cost-intensive.

Another option for manufacturing semiconductor devices is the use ofSOI-wafers which provides for a better dielectric insulation to the bulksubstrate. Again, a comparably thin semiconductor layer is typicallydesired for integrating the devices to reduce parasitic capacitances andto insulate the devices from the bulk material. To produce a thin layer,for example 0.2 μm-10 μm, on a SOI-wafer, a thick semiconductor wafercan be bonded to the SOI-wafer. Before bonding, hydrogen ions areimplanted into a given depth of the thick semiconductor wafer togenerate a separation region. During bonding, or an additional annealingstep, the bonded thick semiconductor wafer splits along the separationregion so that a comparably thin layer remains attached to theSOI-wafer. This technique is known as “smart-cut” which is, however,very cost-intensive due to the hydrogen implantation.

On the other hand, thin seed-layers may be needed for some processes,for example for subsequent epitaxial growth. In some cases,semiconductor material is grown on a carrier of a differentsemiconductor material. After epitaxial growth, the grown layer needs tobe removed from the carrier without causing damage to the epitaxiallayer.

In view of the above, there is a need for improvement.

SUMMARY

According to an embodiment, a method for manufacturing a semiconductorsubstrate includes providing a semiconductor wafer having a firstsurface and a second surface opposite to the first surface; forming,when seen in a cross-section perpendicular to the first surface,cavities in the semiconductor wafer at a first distance from the firstsurface, the cavities being laterally spaced from each other bypartition walls formed by semiconductor material of the wafer, whereinthe cavities form a separation region; forming a semiconductor layer onthe first surface of the semiconductor wafer; breaking at least some ofthe partition walls by applying mechanical impact to the partition wallsto split the semiconductor wafer along the separation region.

According to an embodiment, a method for manufacturing a semiconductorsubstrate includes providing a seed-wafer having a first surface and asecond surface opposite the first surface, wherein the seed-waferincludes semiconductor material exposed at the first surface of theseed-wafer; forming, when seen in a cross-section perpendicular to thefirst surface, cavities in the seed-wafer at a first distance from thefirst surface, the cavities being laterally spaced from each other bypartition walls formed by the semiconductor material of the seed-wafer,wherein the cavities form a separation region; forming an epitaxiallayer on the exposed semiconductor material of the seed-wafer, theepitaxial layer having a thickness which is larger than the firstdistance between the cavities and the first surface of the seed-wafer,and breaking at least some of the partition walls by applying mechanicalimpact to the partition walls to split the semiconductor wafer along theseparation region.

According to an embodiment, a method for manufacturing a semiconductorsubstrate includes providing a seed-wafer having a first surface and asecond surface opposite the first surface, wherein the seed-waferincludes a first semiconductor material exposed at the first surface ofthe seed-wafer; forming, when seen in a cross-section perpendicular tothe first surface, cavities in the seed-wafer at a first distance fromthe first surface, the cavities being laterally spaced from each otherby partition walls formed by the first semiconductor material of theseed-wafer and forming a separation region; depositing, at an elevatedtemperature, a second semiconductor material different to the firstsemiconductor material on the exposed first semiconductor material ofthe seed-wafer, the second semiconductor material having a thicknesswhich is at least 10-times larger than the first distance between thecavities and the first surface of the seed-wafer; and cooling theseed-wafer with the second semiconductor material deposited on the firstsurface of the seed-wafer to cause mechanical stress acting on thepartition walls due to different thermal shrinkage of the firstsemiconductor material and the second semiconductor material, whereinthe mechanical stress results in breaking of at least some of thepartition walls to split at least partially the seed-wafer along theseparation region.

According to an embodiment, a method for manufacturing a semiconductorsubstrate includes providing a first wafer having a first surface and asecond surface opposite the first surface; forming cavitiesinterconnected with each other in the first wafer at a first distancefrom the first surface, wherein the cavities, when seen in across-section perpendicular to the first surface, are laterally spacedfrom each other by partition walls formed by material of the firstwafer, and wherein the cavities form a separation region; forming asemiconductor layer on the first surface of the first wafer; filling thecavities with an aqueous solution; and breaking the partition walls byapplying mechanical impact to the partition walls through the aqueoussolution to split the first wafer along the separation region.

According to an embodiment, a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein includesproviding a seed-wafer having a first surface and a second surfaceopposite the first surface, wherein the seed-wafer includes asemiconductor material exposed at the first surface of the seed-wafer;forming cavities in the seed-wafer at a first distance from the firstsurface, wherein the cavities, when seen in a cross-sectionperpendicular to the first surface, are laterally spaced from each otherby partition walls formed by the semiconductor material of theseed-wafer, and wherein the cavities form a separation region;depositing an epitaxial layer on the exposed semiconductor material ofthe seed-wafer at the first surface of the seed-wafer; at leastpartially integrating semiconductor devices in the epitaxial layer byforming doping regions in the epitaxial layer; and breaking thepartition walls by applying mechanical impact to the partition walls tosplit the seed-wafer along the separation region.

According to an embodiment, a method for manufacturing a semiconductorsubstrate includes providing a first wafer having a first surface and asecond surface opposite the first surface; forming cavities in the firstwafer at a first distance from the first surface, wherein the cavities,when seen in a cross-section perpendicular to the first surface, arelaterally spaced from each other by partition walls formed by thesemiconductor material of the first wafer, and wherein the cavities forma separation region; bonding a second wafer on the first surface of thefirst wafer; breaking the partition walls by applying mechanical impactto the partition walls to split the first wafer along the separationregion so that a residual wafer remains attached to the second wafer;and depositing an epitaxial layer on the residual wafer.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the figures are not necessarily to scale, insteademphasis being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts. In the drawings:

FIG. 1A to 1G illustrate a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein according toan embodiment;

FIG. 2 illustrates an enlarged view of a semiconductor substrate havingcavities formed therein;

FIGS. 3A to 3C illustrate plan views of cavities of semiconductorsubstrates according to various embodiments;

FIGS. 4A to 4D illustrate a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein according toan embodiment;

FIGS. 5A to 5D illustrate a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein according toan embodiment;

FIGS. 6A to 6F illustrate a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein according toan embodiment;

FIG. 7 illustrates an enlarged view of a semiconductor substrate havingcavities formed therein; and

FIGS. 8A to 8C illustrate plane views of cavities of semiconductorsubstrates according to various embodiments.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which are shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top”,“bottom”, “front”, “back”, leading”, “trailing” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purpose ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilised and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims. The embodiments being described use specific language,which should not be construed as limiting the scope of the appendedclaims. The embodiments can be combined unless noted otherwise. Thedrawings are not drawn to scale.

The term “lateral” as used in this specification intends to describe anorientation parallel to a first main surface of a semiconductorsubstrate.

The term “vertical” as used in this specification intends to describe anorientation, which is arranged perpendicular to the first surface of thesemiconductor substrate.

In this specification, a second surface of a semiconductor substrate isconsidered to be formed by the lower or back-side surface while thefirst surface is considered to be formed by the upper, front or mainsurface of the semiconductor substrate. The terms “above” and “below” asused in this specification therefore describe a relative location of astructural feature to another structural feature with consideration ofthis orientation.

With reference to FIGS. 1A to 1G a first embodiment is described. Asemiconductor wafer 100 having a first surface 101 and a second surface102 opposite to the first surface 101 is provided. In this embodiment,the wafer 100 is comprised of Si but could also be comprised of othersemiconductor material such as SiC, SiGe, or sapphire.

In a further process, laterally extending cavities 103, with respect tothe lateral direction parallel to the first surface 101, are formed,when seen in a cross-section perpendicular to the first surface 101, inthe semiconductor wafer 100 at a first distance “a” from the firstsurface 101. The first distance “a” is indicated in FIG. 2. The cavities103 are laterally spaced from each other by partition walls 104 formedby semiconductor material of the wafer 100 as seen in FIG. 1C. Thecavities 103 form a separation region 109 indicated by a dotted line inFIG. 1C.

The cavities 103 can be formed, according to an embodiment, by forming aplurality of groups 112 of closely spaced trenches 108 in the firstsurface 101 of the wafer 100, wherein the trenches 108 extend at leastto a depth from the first surface 101 corresponding to the firstdistance “a”. Typically, the trenches 108 will be formed deeper than thesum of the distance “a” and the height “b” of the cavities 103. Height“b” of the cavities 103 is also indicated in FIG. 2.

The depth of the cavities 103 within wafer 100 can be adjusted, forexample, by the depth of the trenches 108 and also the volume of thehollow trenches 108. Deeper cavities 103, i.e. cavities 103 having acomparably large first distance “d”, can be formed for example bybottle-shaped trenches 108.

For forming the groups 112 of closely spaced trenches 108, a mask 110having openings 111 defining the size and location of the trenches 108to be formed can be formed on the first surface 101 of wafer 100 as seenin FIG. 1B. The trenches 108 are formed, for example, by anisotropicetching using the mask 110 as an etching mask. In a plan view onto thefirst surface 101, the openings 111 may have a circular or ellipsoidcross-section. Other cross-sections such as square-shaped orrectangular-shaped are also possible.

A subsequent tempering of the wafer 100 at an elevated temperature in adeoxidizing atmosphere causes surface migration of the semiconductormaterial of the wafer 100 until the trenches 108 of the respectivegroups 112 of closely spaced trenches 108 coalesce to respectivecavities 103. This is indicated in FIG. 1C.

Referring back to FIG. 1B, the lateral distance x1, x2 between thegroups 112 of closely spaced trenches 108 is larger than the pitch ofthe trenches 108 within a group 112 of closely spaced trenches 108 sothat the trenches of adjacent groups 112 of closely spaced trenches 108do not merge. In fact, between adjacent final cavities 103, each ofwhich is formed by a respective group 112 of closely spaced trenches 108which have coalesced or merged during the tempering, there are partitionwalls 104.

The process conditions during tempering can be adjusted according tospecific needs. For illustration purposes, the temperature can be in arange from about 1000° C. to about 1150° C. In this temperature range,the Si-semiconductor material of the wafer 100 begins to “flow” and thetrenches 108 start to become closed by the flowing material. On theother hand, the trenches 108 widen in the depth due to the flowingmaterial so that closely spaced trenches 108 begin to merge. Whether atrench 108 transforms to a single cavity or adjacent trenches 108 mergeto a common cavity depends on the lateral spacing, i.e. pitch, of thetrenches 108. A cavity formed by a single trench may have a sphericalshape while a cavity formed by a plurality of trenches 108 may have anelongated shape or even plane shape, when seen in a projection onto thefirst surface 101. For example, a rectangular array of closely spacedtrenches 108 form a rectangular cavity (seen in projection onto thefirst surface 101) while a row of closely spaced trenches 108 forms anelongated cavity. Therefore, by selecting the arrangement of thetrenches 108, virtually any cavity arrangement and shape can be formed.

The tempering can be carried out, according to an embodiment, in adeoxidizing atmosphere, for example in a hydrogen atmosphere at lowpressure, for example at about 10 Torr (about 1.3·10³ Pa). The durationof the tempering process can be varied and can be selected in view ofthe temperature. A typical tempering time at the desired temperingtemperature is about 10 min.

Suitable shapes of the formed cavities 103 are illustrated in FIGS. 3Ato 3C which show projections onto the first surface 101. The cavity 103can be a single large cavity 103, or a connected cavity, as shown inFIG. 3A. The cavity 103 is mechanically stabilised by separate partitionwalls 104 formed by pillar-shaped walls as shown in FIG. 3A.Alternatively, separate square or rectangular cavities 103 can be formedwhich are separated from each other by partition walls 104 asillustrated in FIG. 3B. The partition walls 104, and also the cavities103, can also be formed as concentric rings around the geometric centreof the wafer 100 when seen in a projection onto the first surface 101.FIG. 3C illustrates a portion of the wafer showing segments ofconcentrically arranged cavities 103 and partition walls 104.

Hence, according to an embodiment, when seen in a projection onto thefirst surface 101 of the wafer 100, the cavities 103 are ring-shaped andare arranged in a substantially concentric manner.

The partition walls 104 can virtually have any suitable shape and size,for example hexagonal, quadratic or pillar-shaped (point-shaped). Forthe purpose of this embodiment, the area ratio between the cavities 103and the partition walls 104, when seen in a projection onto the firstsurface 101, should be larger than 1, particularly larger than 10, andmore particular larger than 20. The main function of the partition walls104 is to provide sufficient mechanical stability so that the cavities103 do not collapse during further processing. FIG. 2 illustrategeometrical parameters of the cavities 103 and the partition walls 104.Parameter “a” indicates the first distance between the cavities 103 andthe first surface 101 while parameter “e” indicates a second distancebetween the cavities 103 and the second surface 102 of wafer 100.Parameter “b” defines the height of the cavities 103 while parameter “c”defines the lateral width of the cavities 103. Parameter “d” indicatesthe thickness of the partition walls 104 between adjacent cavities 103.

According to an embodiment, the ratio c:b is between about 10:1 to about100:1. The cavities 103 have therefore a small height in comparison totheir lateral extension. This ratio is beneficial for splitting thewafer 100 along the separation region 109 as described further below.

According to an embodiment, the ratio b:d is not higher than 5:1,particularly not higher than 3:1. The partition walls 103 shall not betoo high as they should maintain their mechanical rigidity. This isagain beneficial for a later separation along the separation region 109defined by the cavities 103.

Referring back to FIG. 1B, the lateral distance x1, x2 between adjacentgroups 112 of closely spaced trenches 108 for forming the cavities 103can be equal or different. Furthermore, the lateral “extension” y1, y2of the groups 112 of closely spaced trenches 108 can be equal ordifferent according to specific need. The lateral distance x1, x2determines the lateral thickness d of the final partition walls 104while the lateral “extension” y1, y2 of the groups 112 of closely spacedtrenches 108 determines the lateral width of the cavities 103. It shouldbe noted here that due to the flow of the semiconductor material duringthe tempering process, the initial lateral distance x1, x2 does notexactly correspond to the final thickness of the partition walls 104 andthe lateral “extension” y1, y2 of the groups 112 of closely spacedtrenches 108 does not exactly correspond to the final lateral width ofthe cavities 103. The lateral distance x1, x2 is larger than thedistance between adjacent trenches 108 within a group 112 of closelyspaced trenches 108.

For illustration purposes, a single trench 108 within a group 112 oftrenches 108 may have a depth between about 2 μm to about 5 μm, whenseen in a cross-section perpendicular to the first surface 101, and adiameter between about 0.2 mm to about 1 μm, when seen in a plane viewonto the first surface 101. The pitch within a group of adjacenttrenches 108 of a group 112 of closely spaced trenches 108 may bebetween about 0.4 μm to about 2 μm. Selecting a lateral distance x1, x2larger than, for example 2 μm, prevents the outer trenches 108 ofadjacent groups 112 of closely spaced trenches 108 from merging.Suitable dimensions of the final cavities 103 and partition walls 104are: parameter “a” between about 0.1 μm to about 1 μm; parameter “b”between about 1 μm to about 2 μm; parameter “c” between about 10 μm toabout 100 μm; and parameter “d” between about 1 μm to about 5 μm.

The structure of the wafer 100 after formation of the cavities 103 isillustrated in FIG. 1C. As illustrated there, the cavities 103 areformed closer to the first surface 101 than to the second surface 102 sothat only a comparably thin material layer is left between the cavities103 and the first surface 101.

In a further process, as illustrated in FIG. 1D, a semiconductor layer120 is formed on the first surface 101 of the semiconductor wafer 100.The semiconductor layer 120 can be formed, for example, by epitaxialdeposition. In this case, the wafer 100 is a seed-wafer for theepitaxial layer 120 to be formed. For epitaxial growth, thesemiconductor material of the wafer 100 is at least partially, typicallycompletely, exposed at the first surface 101.

The crystallographic properties of the first surface 101 after formationof the cavities 103 are sufficient to function as a seed layer for anepitaxial growth. This is true for epitaxial growth of the same or of adifferent semiconductor material.

According to an embodiment, the wafer 100 and the epitaxial layer 120are comprised of the same semiconductor material such as Si.

According to another embodiment, the wafer 100 is comprised of a firstsemiconductor material such as Si while the epitaxial layer 120 iscomprised of a different semiconductor material such as GaN. An exposedSi-surface can be used for depositing GaN since both semiconductormaterials have a similar lattice constant. In the present embodimentillustrated in FIGS. 1A to 1F, the epitaxial layer 120 is comprised ofGaN which is deposited on the wafer 100 comprised of Si using suitablyadapted processes.

Since the wafer 100 functions as seed-wafer, it is desirable to removethe wafer 100 from the formed epitaxial layer 120 in a later process.The separation region 109 formed by the cavities 103 will facilitate theseparation. In addition to that, the cavities 103 and the partitionwalls 104 partially mechanically “decouple” the epitaxial layer 120 fromthe wafer 100.

GaN and Si have different coefficients of thermal expansion (Si:2.6·10⁻⁶/° K; GaN: 6·10⁻⁶/° K). Epitaxial deposition occurs at elevatedtemperature, for example at a temperature higher than 800° C., forexample at about 1000° C. During subsequent cooling, mechanical tensionarises in the layer arrangement of the wafer 100 and the epitaxial layer120 due to different thermal shrinkage of the different semiconductormaterials. For example, assume a Si wafer 100 having a size of a 6 inchwafer with a GaN layer 120 deposited thereon at about 1000° C. Aftercooling to ambient temperature, the offset between the outer edges ofthe GaN layer 120 to the Si wafer 100 would be about 250 μm due todifferent shrinkage. However, since the GaN layer 120 and the wafer 100are in 2-dimensional contact with each other, the different shrinkagewill lead to large mechanical stress during cooling which would causecracks in the GaN layer 102.

To avoid large mechanical stress during cooling and to facilitateseparation of the Si wafer 100 from the GaN layer 120, the cavities 103are provided close the first surface 101 of the wafer 100. The cavities103 reduces the cross sectional area of the Si material in the level ofthe separation region 109. During cooling, the GaN layer 120 shrinksfaster than the Si wafer 100. This is most pronounced at the edges ofthe GaN layer 120 and the wafer 100. The mechanical stress caused due tothe different shrinkage is therefore concentrated in the partition walls104 which, however, due to their comparably small height, cannotsufficiently flex to compensate the different shrinkage. As a result,the partition walls 104 break. This will typically start at the outeredge of the GaN layer 102 and the wafer 100 since the lateral offsetbetween the two semiconductor materials will be most pronounced there.The breaking then progresses towards the centre of the wafer 100 uponfurther cooling. Once the layer arrangement of the GaN layer 102 and thewafer 100 is cooled to ambient temperature, most of all of the partitionwalls 104 are broken. Unbroken partition walls 104 can be cut either byetching or by applying a controlled mechanical impact such asultrasound. Suitable embodiments employing ultrasonic sound, which canbe combined with the above embodiments, are described further below.According to an embodiment, a subsequent wet-chemical etching ormechanical processes is carried out for finally splitting the wafer 100along the separation region 109.

The shear stress caused by the different expansion or shrinkage of theGaN layer 120 and the Si wafer 100 and acting on the partition walls 104is amplified approximately by a factor defined by an area ratio, whenseen in a projection onto the first surface 101, between the area of thecavities 103 and the area of the partition walls 104. In many cases,this ratio can be approximated by c/d. Since the semiconductor material“above” the cavities 103 and the semiconductor material “below” thecavities 103 are connected with each other only through the partitionwalls 104, the mechanical stress will concentrate in the partition walls104. The larger the cavities 103 relative to the partition walls 104,the larger the stress acting on the partition walls 104. Forillustration purposes, assume a concentric arrangement of the cavities103 and partition walls 104 as indicated in FIG. 3C. Assume furthermore,that the partition walls 104 have a lateral width “d” of about 2 μmwhile the lateral width “c” of the cavities 103 corresponding to thedistance between adjacent partition walls 104 is about 50 μm. The shearstress acting on the partition walls 104 is then increased by a factorof about 25 in this case. In case of the point-wise arrangement of thepartition walls 104 as illustrated in FIG. 3A and assuming that d isabout 1 μm and c is about 10 μm, the factor would be about 100 or evenhigher since the area covered by the cavities 103 is nearly 100-timeslarger than the area covered by the partition walls 104.

To improve the thermally induced breaking of the partition walls 104,the mechanical properties of the semiconductor material of wafer 100above the cavities 103 should be dominated by the mechanicalcharacteristics of the deposited GaN layer 120. According to anembodiment, the thickness of the epitaxial GaN layer 120 is therefore atleast 10-times larger, typically at least 50-times larger, than thefirst distance “a” between the cavities 103 and the first surface 101 ofthe wafer 100. Hence, the thickness of a Si layer formed by the materialof the wafer 100 above the cavities 103 is significantly smaller thanthe thickness of the epitaxial layer 120.

On the other hand, the mechanical properties of the semiconductormaterial of the wafer 100 below the cavities 103 should be dominated bythe mechanical characteristics of Si. According to an embodiment, thesecond distance “e” is therefore at least 50-times larger than the firstdistance “a”.

As a consequence, at least some or all of the partition walls 104 arebroken when a mechanical impact is applied to the partition walls 104 tosplit the wafer 100 along the separation region 109. In this embodiment,the mechanical impact is the result of the different thermal behaviourof the semiconductor material of the wafer 100 and the semiconductormaterial of the epitaxial layer 120. Additional external impact, forexample by ultrasonic sound, can also be applied.

For illustration purposes, the thickness of the semiconductor materialof the wafer 100 above the cavities 103, which thickness corresponds tothe first distance “d”, can be in a range of about 0.1 μm to about 1 μm.The total thickness of the wafer 100 may be about 500 μm while thethickness “z”, as indicated in FIG. 2, of the epitaxial layer 120 can beabout 50 μm to about 100 μm.

The above described approach allows the formation of comparably thickGaN layers on Si without the risk of cracks within the deposited GaNlayer 120. This is beneficial from the process point of view for severalreasons.

One reason is that a Si-wafer is comparably cheap relative to othersuitable seed material for GaN such as Sapphire or SiC. Furthermore,current technology can only provide 6 inch sapphire or SiC wafers whileSilicon technology is able to provide up to 12 inch wafer. Consequently,the deposited GaN layer would have the same size as the large 12 inch Siwafer and thus allows integration of more devices.

A further reason is that even thick GaN layers can be formed. The Siseed wafer 100 is only used as starting material which is conventionallyremoved before integrating devices into the GaN layer. Hence, a GaNlayer having a thickness sufficient to provide mechanical stability forthe subsequent processes is desired, i.e. the GaN layer 120 separatedfrom the wafer 100 serves as wafer for further processing. Since thecavities 103 mechanically “decouple” the deposited GaN layer 120 fromthe seed wafer 100, thick GaN layer can be formed. Without theseparation region 109 formed by the cavities 103, the thickness of thedeposited GaN layer on Si would be restricted to about 6 μm to avoidcracks in the GaN layer. Hence, GaN layers 120 having a thickness largerthan 6 μm, for example from about 50 μm to about 100 μm can be produced.

Another reason is that the cavities 103 facilitate separation of the GaNlayer 120 from the seed wafer 100 by splitting the seed wafer 100 alongthe separation region 109. Hence, no demanding ion implantation, asneeded by the smart cut technology, must be employed. Furthermore,separation nearly automatically occurs during cooling without anyadditional steps.

Hence, according to an embodiment, a method for manufacturing asemiconductor substrate is provided which includes providing aseed-wafer having a first surface and a second surface opposite thefirst surface, wherein the seed-wafer includes a first semiconductormaterial exposed at the first surface of the seed-wafer. Cavities areformed in the seed-wafer, when seen in a cross-section perpendicular tothe first surface, at a first distance from the first surface, whereinthe cavities are laterally spaced from each other by partition wallsformed by the first semiconductor material of the seed-wafer. Thecavities form a separation region. A further process include depositing,at an elevated temperature, a second semiconductor material different tothe first semiconductor material on the exposed first semiconductormaterial of the seed-wafer with a thickness which is at least 10-timeslarger than the first distance between the cavities and the firstsurface of the seed-wafer. A further process includes cooling theseed-wafer with the second semiconductor material deposited on the firstsurface of the seed-wafer to cause mechanical stress acting on thepartition walls due to different thermal shrinkage of the firstsemiconductor material and the second semiconductor material, whereinthe mechanical stress results in breaking of at least some of thepartition walls to split at least partially the seed-wafer along theseparation region.

The shear strain caused by the different thermal deformation of thefirst and second semiconductor material is partially or completely“absorbed” by the partition walls which will break. The secondsemiconductor material can therefore be comparably thick without therisk that cracks occur in the second semiconductor material.

FIG. 1E illustrates the situation after cooling and breaking of thepartition walls 104. The final different lateral extension of theepitaxial layer 120 and the wafer 100 is also illustrated.

According to another embodiment, a method for manufacturing asemiconductor substrate is provided which includes providing aseed-wafer having a first surface and a second surface opposite thefirst surface, wherein the seed-wafer is comprised of a semiconductormaterial exposed at the first surface of the seed-wafer. Cavities areformed in the seed-wafer, when seen in a cross-section perpendicular tothe first surface, at a first distance from the first surface, whereinthe cavities are laterally spaced from each other by partition wallsformed by the semiconductor material of the seed-wafer. The cavitiesform a separation region. An epitaxial layer is formed on the exposedsemiconductor material of the seed-wafer with a thickness which islarger than the first distance between the cavities and the firstsurface of the seed-wafer. At least some of the partition walls arebroken by applying mechanical impact to the partition walls to split thesemiconductor wafer along the separation region.

According to an embodiment and as shown in FIG. 1E, a residual wafer 100a remains attached to the epitaxial layer 120 after breaking of thepartition walls 104. The residual wafer 100 a is formed by the materialof the wafer 100 which remains in contact with the epitaxial layer 120and which is predominantly formed by the semiconductor material abovethe cavities 103.

In a further process, the epitaxial layer 120 is processed at the sidewhere the residual wafer 100 a remains attached, for example bypolishing, grinding or etching. The residual wafer 100 a may only bepolished to provide a smooth surface or may be completely removed asillustrated in FIG. 1F. As a result, the epitaxial layer 120 has a firstsurface 121, which was the originally upper and exposed surface of theepitaxial layer 120, and a processed second surface 122 a.

Furthermore, the wafer 100 can also be polished at its side where thecavities 103 were formed to obtain a smooth processed first surface 101a. The wafer 100 can then be re-used as a seed-wafer, includingformation of cavities as described above.

In a further process, as illustrated in FIG. 1G, semiconductor devices150 are integrated in the epitaxial layer 120, in this case at the firstsurface 121, by forming at least one doping region 151, 152. Forexample, power GaN devices such as FETs, IGBTs, and diodes, to name afew, can be integrated either as lateral devices or as vertical devices.

In a further process, individual semiconductor devices 150 can beseparated from each other along vertical cut lines 160 as indicated inFIG. 1G.

In the above described embodiment, the semiconductor devices 150 areintegrated after splitting of the wafer 100 and optional removal of theresidual wafer 100 a. This is particular beneficial for cases when theepitaxial layer 120 is made of a semiconductor material different to thesemiconductor material of wafer 100.

The above described approach can be applied to any combination ofsemiconductor material irrespectively, whether the wafer 100 or theepitaxial layer 120 has the higher or lower coefficient of thermalexpansion. Mechanical tensions which develop between the differentsemiconductor materials, either during deposition, cooling, heating ordue to other reasons, will be absorbed by the irreversible deformationand final break of the partition walls 104.

The above described embodiments made use of intrinsically occurringmechanical tensions caused by the thermal deformation of differentsemiconductor materials. In further embodiments, externally inducedmechanical tensions are used for breaking the partition walls.

With reference to FIGS. 4A to 4D, a further embodiment is describednext.

A first wafer 200 having a first surface 201 and a second surface 202opposite the first surface 201 is provided. The first wafer 200 is madein this embodiment of Si but can also be made of other semiconductormaterials such as SiC, SiGe, sapphire, and GaN to name a few. Cavities203 are formed as described previously herein. In this embodiment, thecavities 203 are interconnected with each other in the first wafer 200and are arranged, similar to the above embodiments, at a first distance“a” from the first surface 201. The cavities 203, when seen in across-section perpendicular to the first surface 201, are laterallyspaced from each other by partition walls 204 formed by material of thefirst wafer 200. Similar to the embodiments previously described herein,the cavities 203 form a separation region 209. Formation of the cavities203 can be carried out as previously described herein. Therefore, thedetailed description of the cavity formation process is omitted here.FIG. 4A shows the first wafer 200 having laterally extending cavities203.

In a further process, a semiconductor layer 220 is formed on the firstsurface 201 of the first wafer 200. The semiconductor layer 220 caneither be an epitaxial layer or a bonded layer. The thickness and thedoping of the semiconductor layer 220 can be selected according tospecific needs. In case of epitaxial deposition, the first wafer 200serves as a seed-wafer.

In a further process, the cavities 203 are filled with an aqueoussolution 206 such as pure water as illustrated in FIG. 4B.

In a further process, the partition walls 204 are broken by applyingmechanical impact to the partition walls 204 through the aqueoussolution 206 to split the first wafer 200 along the separation region209. The mechanical impact can be generated, for example, throughexpansion of the aqueous solution 206 within the cavities 203 or throughultrasonic sound supplied to the aqueous solution 206.

According to an embodiment, the aqueous solution 206 has a freezingpoint. In case of pure water the freezing point is 0° C. For breakingthe partition walls 204 the aqueous solution 206 is cooled in theinterconnected cavities 203 below the freezing point to cause expansionof the aqueous solution 206. Typically, the wafer 200 together with thesemiconductor layer 220 is cooled below the freezing point. The aqueoussolution 206 begins to freeze and expand. This expansion generates alarge mechanical impact which finally leads to cracks and breaks withinthe partition walls 204 as the partition walls 204 are the weakestmechanical element due to their small cross-section area. The partitionwalls 204 are disrupted due to the expanding frozen aqueous solution206.

According to an embodiment, a hydrophilic layer 270 is formed oninternal surfaces of the cavities 203 prior to filling the cavities 203with the aqueous solution 206. This is illustrated in FIG. 4A. Thehydrophobic layer 270 facilitates filling of the cavities 203 with theaqueous solution 206 which would be difficult if the semiconductormaterial of the first wafer 200 is hydrophobic.

According to an embodiment, the hydrophilic layer 270 is formed byoxidising the internal surfaces of the cavities 203. This can be done atany time between formation of the cavities 203 and filling with theaqueous solution 206. The hydrophilic layer 270 causes large capillaryforces acting on the aqueous solution 206 which suck the aqueoussolution 206 into the cavities 203. Since the cavities 203 areinterconnected with each other, all cavities 203 are filled.

To prevent gas bubbles, the first wafer 200 can be first subjected to avacuum to remove gas from the cavities 203 followed by immersion of thefirst wafer 200 into the aqueous solution 206. It is beneficial to keepthe vacuum conditions during filling.

According to an embodiment, at least one semiconductor device 250,typically a plurality of semiconductor devices 250 is integrated intothe semiconductor layer 220 before splitting the first wafer 200 byforming at least one doping region 251, 252. This is illustrated in FIG.4C. The semiconductor layer 220 is in contact with the first wafer 200during partial or complete integration of the semiconductor devices 250.The first wafer 200 functions as a carrier wafer for the semiconductorlayer 220 if the semiconductor layer 220 is not mechanically stable byitself. Hence, the semiconductor layer 220 can be thinner than the firstwafer 200.

The semiconductor layer 220 includes an exposed first surface 221 and asecond surface 222 which is in contact with the first surface 201 of thefirst wafer 200. Integration of the semiconductor devices 250 occurs atleast at the first surface 221 of the semiconductor layer 220.

After partial or complete integration of the semiconductor devices 250,the first wafer 200 is split along the separation region 209 asdescribed above and shown in FIG. 4C. Similar as previously describedherein, a residual wafer 200 a remains attached to the second surface222 of the semiconductor layer 220. The residual wafer 200 a can befinally removed or only polished. FIG. 4D shows the case of a completelyremoved residual wafer 200 a. In this case the semiconductor layer 220has a processed second surface 222 a at which further structures of thesemiconductor devices 250 can be integrated.

Similar as previously described herein, the first wafer 200 can bepolished or grinded at its first surface 201 to flatten this surfaceafter splitting to have a flat processed first surface 201 a. The firstwafer 200 can then be re-used.

In view of the above, a method for manufacturing a semiconductorsubstrate having semiconductor devices integrated therein includesproviding a seed-wafer 200 having a first surface 201 and a secondsurface 202 opposite the first surface 201. The seed-wafer 200 includesa semiconductor material exposed at the first surface 201 of theseed-wafer 200. Cavities 203 are formed in the seed-wafer 200 at a firstdistance from the first surface 201, wherein the cavities 203 when seenin a cross-section perpendicular to the first surface 201, are laterallyspaced from each other by partition walls 204 formed by thesemiconductor material of the seed-wafer 200. The cavities 203 form aseparation region 209. An epitaxial layer 220 is deposited on theexposed semiconductor material 200 of the seed-wafer 200 at the firstsurface 201 of the seed-wafer. Semiconductor devices 250 are at leastpartially integrated in the epitaxial layer 220 by forming dopingregions 251, 252 in the epitaxial layer 220. The partition walls 204 arebroken by applying mechanical impact to the partition walls 204 to splitthe seed-wafer 200 along the separation region 209.

According to an embodiment, the cavities 203 are interconnected witheach other and filled with an aqueous solution 206 having a freezingpoint. Breaking the partition walls 204 includes cooling the aqueoussolution 206 in the cavities 203 below the freezing point to causeexpansion of the aqueous solution 206 which will break the partitionwalls 204.

Different to the embodiment illustrated in FIGS. 1A to 1G, integrationof the semiconductor devices 250 starts before splitting the first waferor seed-wafer 200.

In a further embodiment, the partition walls 204 are subjected tomechanical stress by applying ultrasonic sound to the aqueous solution206. Hence, instead of cooling, ultrasonic sound is coupled into thefirst wafer 200, typically from the second surface 202. According to anembodiment, the aqueous solution 206 in the cavities 203 is subjected toultrasonic sound to cause cavitation of the aqueous solution 206.Cavitation may lead to gas bubbles which generate a pressure within thecavities 203. As a result, the cavities 203 burst, similar as in thecase of the freezing aqueous solution 206 leading to broken partitionwalls 204. The first wafer 200 is thus split along the predefinedseparation region 209.

Cavitation causes extreme local effects such as flows having a velocityof up to 1000 km\h, pressures of up to 2000 bar, and temperatures of upto 4500° C. These extreme local effects cause mechanical failure of thepartition walls 204 and hence delamination of the first wafer 200. Togenerate cavitation, the frequency and energy of the supplied ultrasonicsound can be suitably selected. Furthermore, ultrasound application canbe combined with other liquids as well which undergo cavitation whensubjected to ultrasound.

Application of ultrasound can be combined with any other separationapproach described herein.

In an alternative embodiment, ultrasound is supplied without havingfilled the cavities 203 with the aqueous solution 206. The ultrasonicsound can be supplied, for example, from the second surface 202 of thefirst wafer 200. Due to the restricted cross-sectional area of thepartition walls 204, the ultrasound is concentrated in the partitionwalls 204 in the level of the separation region 209 and hence theultrasonic sound energy is also focussed into the partition walls 204.As a result, the partition walls 204 will break. The energy increase inthe partition walls 204 is approximately equal to the area ratio betweenthe cavities 203 and the partition walls 204 as described previouslyherein, and is typically in the range between 10 and 100.

With reference to FIGS. 5A to 5D a further embodiment is described next.Similar as with the embodiment of FIGS. 4A to 4D, a seed-wafer 200having a first surface 201 and a second surface 202 opposite to thefirst surface 201 is provided, wherein the seed-wafer 200 includes asemiconductor material exposed at the first surface 201 of theseed-wafer. Cavities 203 are formed in the seed-wafer 200 at a firstdistance from the first surface 201. The cavities 203, when seen in across-section perpendicular to the first surface 201, are laterallyspaced from each other by partition walls 204 formed by thesemiconductor material of the seed-wafer 200. The cavities 203 form aseparation region 209. In a further process, an epitaxial layer 220 isdeposited on the exposed semiconductor material 200 of the seed-wafer200 at the first surface 201 of the seed-wafer 200. In a furtherprocess, semiconductor devices 250 are at least partially integrated inthe epitaxial layer 220 by forming doping regions 251, 252 in theepitaxial layer 220. The resulting structure is illustrated in FIG. 5Awhich substantially corresponds to the structure illustrated in FIG. 4B,with the exception that the cavities 203 are not filled with an aqueoussolution.

After partial or complete integration of the semiconductor devices 250,vertical separation trenches 261 extending from the first surface 221 ofthe epitaxial layer 220 at least as far as to the cavities 203 areformed between the semiconductor devices 250. The separation trenches261 serve as vertical cut regions for individualizing the semiconductordevices 250.

The separation trenches 261 can be formed, for example, by plasmaetching or laser cutting. The depth of the separation trenches 261should be at least as far as the cavities 203 and is typically deeperthan the cavities 203. The separation trenches 261 are formed from thefirst surface 221 of the epitaxial layer 220 to ensure that theepitaxial layer 220, which is the layer used for integrating thesemiconductor devices 250, is cleanly cut. The structure after formationof the separation trenches 261 is illustrated in FIG. 5B. Thesemiconductor devices 250 are now individualized and form respectivesingle chips which are still in contact with each other through theseed-wafer 200.

The individualized chips, which are still connected with each other, canbe grabbed by suitable tools such as pick-and-place tools 280 adapted tohandle semiconductor chips. Either the remaining contact to theseed-wafer 200 will break due to this mechanical handling or ultrasonicsound can be additionally supplied, for example through the suitablyadapted pick-and-place tool 280. Alternatively, a separate ultrasonictransmitter 240 can be provided which, for example, supplies ultrasonicsound from the second surface 202 of the seed-wafer 200. In either case,the partition walls 204 experience mechanical impact which causesdisruption of the partition walls 204. Hence, the partition walls 204are broken by applying mechanical impact to the partition walls 204 tosplit the seed-wafer 200 along the separation region 209. This isillustrated in FIG. 5C with a first chip already transferred to anotherplace, for example placed on a lead frame.

With reference to FIGS. 6A to 6F, a further embodiment is describednext. A first wafer 300 having a first surface 301 and a second surface302 opposite to the first surface 301 is provided. The first wafer 300is comprised of Si but can also be comprised of other semiconductormaterial. Cavities 303 are formed in the first wafer 300 at a firstdistance from the first surface 301. The cavities 303, when seen in across-section perpendicular to the first surface 301, are laterallyspaced from each other by partition walls 304 formed by thesemiconductor material of the first wafer 300. The cavities 303 form aseparation region 309. The resulting structure is substantially the sameas after the processes indicated in FIGS. 1A to 10C so that reference ismade to the corresponding description above for further details.

In a further process, a second wafer 320 is bonded on the first surface301 of the first wafer 300. The second wafer 320 is comprised of Si andcan include a bonding layer 330 in contact with a second surface 322 ofthe second wafer 320. The second wafer 320 also includes a first surface321. The bonding layer 330 can also be formed on the first surface 301of the first wafer 300. Alternatively, bonding can be carried outwithout any bonding layer. Typically, the bonding layer 330 is aninsulating layer such as a silicon oxide layer. The structure situationafter bonding the second wafer 320 onto the first wafer 300 isillustrated in FIG. 6A.

In a further process, the partition walls 304 are disrupted by applyingmechanical impact to the partition walls 304 to split the first wafer300 along the separation region 309. A residual wafer 300 a remainsattached to the second wafer 320, wherein the residual wafer 300 a isformed by material of the first wafer 300 above the cavities 303. i.e.between the cavities 303 and the first surface 301 of the first wafer300. The resulting structure is illustrated in FIG. 6C.

According to an embodiment, splitting the first wafer 300 is carried outaccording to any of the separation methods previously described herein.For example, the cavities 303 are formed such that they areinterconnected with each other. An aqueous solution 306 having afreezing point is then filled into the cavities 303. Subsequent coolingof the aqueous solution 306 in the cavities 303 below the freezing pointcauses the partition walls 304 to break due to the expansion of theaqueous solution 306 within the cavities 303. To facilitate filling thecavities 303 with the aqueous solution 306, a hydrophilic layer 370,such as an oxide layer, can be formed on internal surfaces of thecavities 303 prior to filling the cavities 303 with the aqueous solution306.

Alternatively, the aqueous solution 306 in the interconnected cavities303 is subjected to ultrasonic sound to cause cavitation of the aqueoussolution 306 as previously described herein. This is illustrated in FIG.6B using a separate ultrasonic transmitter 340.

In a further process, as illustrated in FIG. 6D, the residual wafer 300a is polished to have a flat processed surface 307. Any suitable methodcan be used for processing the residual wafer 300 a.

The residual wafer 300 a, which is mechanically supported by the secondwafer 320, is then used as a seed-layer for a subsequent epitaxialdeposition as illustrated in FIG. 6E which shows the second wafer 320with the residual wafer 300 a bonded thereto upside down.

An epitaxial layer 380 is grown on the residual wafer 300 a as shown inFIG. 6E. The epitaxial layer 380 has a first surface 321 and serves asactive layer for integrating semiconductor devices. The buried bondinglayer 330 serves as a buried insulation layer so that, using the aboveprocesses, a SOI-wafer having a use-layer (epitaxial layer 380) with adesired thickness and background doping is manufactured. The SOI-waferis formed by the epitaxial layer 380, residual wafer 300 a, insulatingbonding layer 330 and second wafer 320.

In a further process, as illustrated in FIG. 6F, semiconductor devices350 are at least partially integrated in the epitaxial layer 380 byforming doping regions 351, 352 in the epitaxial layer 380. Afterpartial or complete integration of the semiconductor devices 350, thesemiconductor devices 350 are individualized by cutting the SOI-waferalong cut lines 360 indicated by dashed lines in FIG. 6F.

The geometrical relations of the cavities 303 and partition walls 304can be the same in this embodiment as in the embodiment illustrated inFIGS. 1A to 1G. FIG. 7 shows the geometrical relations using the sameparameters as in FIG. 2.

FIGS. 8A to 8C show embodiments of interconnected cavities 300 which canbe used in any of the above embodiments and specifically in thoseembodiments which uses the aqueous solution. FIG. 8A basicallycorresponds to FIG. 3A since there is only one large cavity 303. InFIGS. 8B and 8C, the adjacent cavities 303 are interconnected with eachother by interconnections 305 which are basically formed by openings inthe partition walls 304. The interconnections 305 are formed such thatadditional trenches 108 are provided between adjacent groups 112 ofclosely spaced trenches 108. For details, reference is made to thedescription of the processes illustrated in FIGS. 1A to 1C. Theinterconnection 305 can be arranged at any location as long as theyensure that all, or at least most of the cavities 303 can be reliablyfilled with the aqueous solution 306.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

What is claimed is:
 1. A method for manufacturing a semiconductorsubstrate, the method comprising: providing a seed-wafer having a firstsurface and a second surface opposite the first surface, the seed-wafercomprising a first semiconductor material exposed at the first surfaceof the seed-wafer; forming, when seen in a cross-section perpendicularto the first surface, cavities in the seed-wafer at a first distancefrom the first surface, the cavities being laterally spaced from eachother by partition walls formed by the first semiconductor material ofthe seed-wafer, the cavities forming a separation region; depositing, atan elevated temperature, a second semiconductor material different tothe first semiconductor material on the exposed first semiconductormaterial of the seed-wafer, the second semiconductor material having athickness which is at least 10-times larger than the first distancebetween the cavities and the first surface of the seed-wafer; andcooling the seed-wafer with the second semiconductor material depositedon the first surface of the seed-wafer to cause mechanical stress actingon the partition walls due to different thermal shrinkage of the firstsemiconductor material and the second semiconductor material, whereinthe mechanical stress results in breaking of at least some of thepartition walls to split at least partially the seed-wafer along theseparation region.
 2. The method of claim 1, wherein the cavities arespaced from the second surface of the seed-wafer by a second distancewhich is at least 10-times larger than the first distance.
 3. The methodof claim 1, wherein the partition walls between adjacent cavities have alateral thickness d and the cavities have a height b, wherein the ratiob:d is 5:1 or less.
 4. The method of claim 3, wherein the ratio b:d is3:1 or less.
 5. The method of claim 1, wherein the cavities have aheight b and a lateral width c, wherein the ratio c:b is between about10:1 and about 100:1.
 6. The method of claim 1, wherein, when seen in aprojection onto the first surface of the seed-wafer, the cavities arering-shaped and arranged in a substantially concentric manner.
 7. Themethod of claim 1, wherein forming the cavities comprises: forming aplurality of groups of closely spaced trenches in the first surface ofthe seed-wafer, the trenches extending at least to a depth from thefirst surface corresponding to the first distance; and tempering theseed-wafer at an elevated temperature in a deoxidising atmosphere tocause surface migration of the first semiconductor material of theseed-wafer until the trenches of the respective groups of closely spacedtrenches coalesce to respective cavities.
 8. The method of claim 7,wherein the elevated temperature is between about 1000° C. and about1150° C.
 9. The method of claim 1, wherein the first semiconductormaterial is silicon and the second semiconductor material is one of GaN,sapphire, and SiC.
 10. The method of claim 1, wherein a residual waferremains attached to the epitaxial layer after breaking of the partitionwalls, the method further comprising: removing the residual wafer fromthe epitaxial layer.
 11. The method of claim 1, further comprising:integrating at least one semiconductor device into the epitaxial layerafter splitting the seed-wafer by forming at least one doping region.12. A method for manufacturing a semiconductor substrate, the methodcomprising: providing a first wafer having a first surface and a secondsurface opposite the first surface; forming cavities in the first waferat a first distance from the first surface, wherein the cavities, whenseen in a cross-section perpendicular to the first surface, arelaterally spaced from each other by partition walls formed by thesemiconductor material of the first wafer, the cavities forming aseparation region; bonding a second wafer on the first surface of thefirst wafer; breaking the partition walls by applying mechanical impactto the partition walls to split the first wafer along the separationregion so that a residual wafer remains attached to the second wafer;and depositing an epitaxial layer on the residual wafer.
 13. The methodof claim 12, further comprising: at least partially integratingsemiconductor devices in the epitaxial layer by forming doping regionsin the epitaxial layer.
 14. The method of claim 13, further comprising:polishing the residual wafer prior to depositing the epitaxial layer.15. The method of claim 13, wherein the cavities are interconnected witheach other, the method further comprising: filling the cavities with anaqueous solution having a freezing point; and breaking the partitionwalls by cooling the aqueous solution in the cavities below the freezingpoint to cause expansion of the aqueous solution.
 16. The method ofclaim 15, further comprising: forming a hydrophilic layer on internalsurfaces of the cavities prior to filling the cavities with the aqueoussolution.
 17. The method of claim 13, wherein the cavities areinterconnected with each other, the method further comprising: fillingthe cavities with an aqueous solution; and breaking the partition wallsby subjecting the aqueous solution in the cavities to ultrasonic soundto cause cavitation of the aqueous solution.
 18. The method of claim 13,wherein the second wafer comprises a bonding layer, wherein bonding thesecond wafer on the first surface of the first wafer comprises: bondingthe second wafer with its bonding layer on the first surface of thefirst wafer.